Semiconductor device having different fin widths

ABSTRACT

A semiconductor device includes at least one source region and at least one drain region. A plurality of fins extend between a source region and a drain region, wherein at least one fin has a different width than another fin. At least one gate is provided to control current flow through such fins. Fin spacing may be varied in addition to, or alternative to utilizing different fin widths.

RELATED APPLICATIONS

This patent application is a Continuation of U.S. application Ser. No.12/484,682, filed on Jun. 15, 2009, which claims the benefit ofpriority, under 35 U.S.C. Section 119(e), to U.S. Provisional PatentApplication Ser. No. 61/073,183, filed on Jun. 17, 2008, whichapplications are incorporated herein by reference in their entirety.

TECHNICAL FIELD

Embodiments described herein relate generally to semiconductor circuitswhich include multi-gate field effect transistor devices.

BACKGROUND

Semiconductor devices such as multi-gate field effect transistors areoften designed for applications using circuits with down-scaled,extremely small devices. Semiconductor devices used for analog and RFapplications may require different device characteristics compared tothose used in digital applications. Harmonic distortion of signals inamplifier circuits increases with signal amplitude and limits thedynamic range of these circuits. Flicker noise (also referred to as 1/fnoise) may depend on properties of fin surfaces in multi-gate fieldeffect transistors and limits resolution in analog and RF circuits. Gateresistance limits gain and increases noise in RF circuits. While theoptimization of the ON/OFF currents for digital circuits is the maintarget during process development, an improvement of analog transistorcharacteristics without process changes is desirable for mixed signaland RF circuits.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A illustrates a perspective view of a semiconductor device havingdifferent fin widths, according to some embodiments of the invention.

FIG. 1B illustrates a perspective view of a semiconductor device havinga different fin widths and gate dimensions, according to someembodiments of the invention.

FIG. 2A illustrates a top view of a semiconductor device havingdifferent fin widths, according to some embodiments of the invention.

FIG. 2B illustrates a top view of a semiconductor device havingdifferent fin widths and gate dimensions, according to some embodimentsof the invention.

FIG. 2C illustrates a top view of a semiconductor device havingdifferent fin widths and gate dimensions, according to some embodimentsof the invention.

FIG. 2D illustrates a top view of a semiconductor device havingdifferent fin widths and gate dimensions, according to some embodimentsof the invention.

FIG. 2E illustrates a top view of a semiconductor device havingdifferent fin widths and gate dimensions, according to some embodimentsof the invention.

FIG. 3A illustrates a perspective view of a gate finger showing lumpedresistance elements representing the distributed nature of the gateresistance when operated at RF frequencies.

FIG. 3B illustrates a perspective view of a cross section through thegate finger of FIG. 3A showing a gate material stack.

FIG. 3C illustrates a top view of a semiconductor device havingdifferent fin spacing, according to some embodiments of the invention.

FIG. 3D illustrates a top view of a semiconductor device havingdifferent fin spacing and gate contacts on two ends, according to someembodiments of the invention.

FIG. 3E illustrates a top view of a semiconductor device havingdecreasing fin widths away from the gate contact, according to someembodiments of the invention.

FIG. 3F illustrates a top view of a semiconductor device having gatecontacts at opposite ends of the device and fin widths decreasingtowards the center of the device, according to some embodiments of theinvention.

FIG. 3G illustrates a top view of a semiconductor device havingincreasing fin widths away from the gate contact, according to someembodiments of the invention.

FIG. 3H illustrates a top view of a semiconductor device having gatecontacts at opposite ends of the device and fin widths increasingtowards the center of the device, according to some embodiments of theinvention.

FIG. 4 illustrates a top view of a semiconductor device having a steppedfin-width structure, according to some embodiments of the invention.

FIG. 5 illustrates a top view of a semiconductor device having a steppedfin-width structure and a split gate structure, according to someembodiments of the invention.

FIG. 6A illustrates a top view of a semiconductor device having astepped fin structure with a narrow fin width in the center of the fin,according to some embodiments of the invention.

FIG. 6B illustrates a top view of a semiconductor device having astepped fin structure with a broad fin width in the center of the fin,according to some embodiments of the invention.

FIG. 6C illustrates a top view of a semiconductor device having astepped fin structure having sections with different fin widths andseparate gates for each of the different fin sections connected to thesame gate signal or connected to different gate signals, according tosome embodiments of the invention.

FIG. 6D illustrates a top view of a semiconductor device having astepped fin structure with a broad fin width in the center of the finand tapered transitions of the fin width from the center to narrower finwidth at source and drain ends.

FIG. 7 illustrates the semiconductor device shown in FIG. 6A with a gatehaving a skewed gate arrangement disposed on the fin, according to someembodiments of the invention.

FIG. 8A illustrates a top view of a semiconductor device showing a finstructure having a tapered section, according to some embodiments of theinvention.

FIG. 8B illustrates a top view of a semiconductor device showing a finstructure having a tapered section, according to some embodiments of theinvention.

FIG. 9 illustrates a top view of a semiconductor device showing a finstructure having a curved section, according to some embodiments of theinvention.

FIG. 10 illustrates a top view of a semiconductor device showingmultiple fins having a stepped fin structure and multiple gatesoverlying the fins, according to some embodiments of the invention.

FIG. 11 illustrates a top view of two semiconductor devices coupled inseries with each device having different fin widths, according to someembodiments of the invention.

FIG. 12A illustrates a top view of two semiconductor device coupled inparallel showing a shared gate between the two devices, according tosome embodiments of the invention.

FIG. 12B illustrates a top view of two semiconductor device coupled inparallel with separate gates controlling the devices, according to someembodiments of the invention.

FIG. 13 illustrates generally an example semiconductor device.

DETAILED DESCRIPTION

The following detailed description refers to the accompanying drawingsthat show, by way of illustration, specific details and embodiments inwhich the invention may be practiced. These embodiments are described insufficient detail to enable those skilled in the art to practice theinvention. Other embodiments may be utilized and structural, logical,and electrical changes may be made without departing from the scope ofthe invention. The various embodiments are not necessarily mutuallyexclusive, as some embodiments can be combined with one or more otherembodiments to form new embodiments. In this document, the terms “a” or“an” are used, as is common in patent documents, to include one or morethan one. In this document, the term “or” is used to refer tononexclusive or, such that “A or B” includes “A but not B,” “B but notA,” and “A and B,” unless otherwise indicated.

The term “substrate” is understood to include a semiconductor wafer. Theterm “substrate” is also used to refer to semiconductor structuresduring processing and may include other layers that have been fabricatedthereupon. Both “wafer” and “substrate” includes doped and undopedsemiconductors, epitaxial or non epitaxial semiconductor layerssupported by a base semiconductor or insulator, as well as othersemiconductor structures well known to one skilled in the art.

The term “multiple gate field effect transistor” (MuGFET) is usedinterchangeably with FinFET herein for the general class ofsemiconductor devices having non-planar field effect transistors formedon fins of semiconductor material having two, three, five or more planesfor conducting channels.

The term “conductor” is understood to generally include n-type andp-type semiconductors and the term “insulator” or “dielectric” isdefined to include any material that is less electrically conductivethan the materials referred to as “conductors.” The invention describedhere is generally related to MuGFET or FinFET transistors. The followingdetailed description is, therefore, not to be taken in a limiting sense.

The harmonic distortion of signals in amplifier circuits increases withsignal amplitude and therefore limits the dynamic range of suchcircuits. A significant portion of distortion is due to the thirdharmonics. This is due to the fact that the frequencies in range ofthird harmonics are in the vicinity of the signal frequencies andconsequently cannot be suppressed by filtering. Such third harmonics aregenerated by the third order derivative of the transistor transfercharacteristics of drain current Id with respect to gate voltage Vg,namely:

g3=∂³ Id/∂Vg ³

One of the design parameter that can be controlled by varying the layoutof a semiconductor device is the width of the silicon fin. Changing thefin width can result in the change in threshold voltage which occurs dueto quantum confinement and electrostatic effects. Changing the width offins can also change the effective mobility and flicker noise of aFinFET device because of different surface roughness of top and sidewall surfaces of a fin and due to different crystal orientations in topand sidewall surfaces of the fin. This is because mobility and flickernoise depends on surface roughness and surface orientation. In someembodiments, semiconductor devices described herein includes embodimentshaving fins with different crystal surface orientations in differentplanes of the fin. The embodiments described herein use the fin widthdependent threshold voltage (Vt), mobility and flicker noise bycombining multiple fins with different width in one transistor structureor a transistor structure consisting of a group of individualtransistors connected by metal wiring to improve the electricalcharacteristics. This combination of different fin width can be done intwo ways, to optimize different transistor characteristics. First, it ispossible to use different fin width in a parallel configuration, togenerate a transistor with modulated threshold voltages and so abroadened threshold voltage range. This results in a reduced harmonicdistortion, as nonlinearities of the transistor transfer curves aresmoothed by a piecewise linearization of the transistor characteristicwith each fin having a different threshold voltage. Second, it ispossible to use different fin width in a series configuration along thelength of the fin (means channel length of the transistor) to improveelectrical characteristics, like drain/source series resistance,transconductance (gm), output conductance (gds), voltage gain (=gm/gds),drain capacitance or flicker noise.

A transistor structure combining different fin widths in parallel may beused also as a tunable capacitance (for example, a varactor) when drainand source pads are connected together to one electrical tune port. Inthis case the broadened threshold voltage due to different fin widthsbroadens the transition from a low capacitance to a high capacitance,which means the derivative of capacitance versus gate to tune portvoltage decreases and so the tuning sensitivity in a voltage controlledoscillator (VCO) gets smaller and more linearized which reduces upconversion of flicker noise into VCO phase noise. Device structuresdescribed herein that combine different fins in parallel may be used astransistors or varactors (unless stated otherwise). Varactors may beformed from transistors by connecting drain and source of the transistortogether.

Fin width variations in an integrated circuit may be introduced indifferent ways. For example, fin width variation may be introducedintentionally using a controlled process. This may be done, for example,by layout drawing or placement in different locations of the layout ofthe integrated circuit having different printing resolution or adedicated processing generating large local fin width mismatchvariations leading to different fin widths. In an embodiment, the widthsof two fins may differ by more than 4 nm (nano meter). In an embodiment,the widths two fins may differ by more than 5 nm. In another embodiment,the widths of two fins may differ by more than 6 nm. In an embodiment,the widths of two fins may differ by more than 7 nm. In an embodiment,the widths of two fins may differ by more than 5 nm. In an embodiment,the widths of two fins may differ by more than 9 nm. In an embodiment,the widths of two fins may differ by more than 10 nm.

Additionally, in some embodiments, it is also possible to change the finwidth in a step like fashion along the fin length. Changing the finwidth in a series configuration along the channel length in a step likefashion can result in an improved output conductance and an improvedvoltage gain (gm/gds), if the fin width resulting in a lower thresholdvoltage (Vt) (which can be different for N-type and P-type devices, forexample NMOS and PMOS transistors) is located at the drain side of thedevice (self-cascoding effect). In some embodiments, placing the narrowfin section at the drain and the wider fin at the source, results in adevice having a lower source resistance improving the transconductance.Additionally, such a device can have a reduced drain induced barrierlowering effect and reduced short channel effect compared to a wide finonly device that improves the output conductance. An increased drainresistance due to the narrower fin on the drain side is acceptable dueto its small effect on transconductance.

In high frequency circuits the gate resistance plays an important rolebesides the already mentioned analog performance figures of merit. FIG.3A presents the distributed gate resistance in a gate finger. This gatefinger usually consists of a material stack. The stack can consist oftwo, three or more different materials. A conventional two materialstack is poly silicon on top of the gate dielectric of the MOS devicecaptured by an above silicide layer. In high-k metal gate devices thegate material stack consists in some embodiments of a metal on top ofthe gate dielectric followed by poly silicon which is caped by asilicide layer as shown in FIG. 3B. Between silicon and metal occurs anSchottky contact resistance that together with the conductivities of thematerials of the stack establishes a vertical gate resistance RV shownin FIG. 3A. Compared to this vertical gate resistance there exists alsoa lateral gate resistance RL (also shown in FIG. 3A) that originatesfrom the resistances of the silicide capping layer in FIG. 3B which isconnected by a gate contact. Due to the high frequencies the resistanceof the gate finger needs to be represented by a distributed gateresistance network as shown in FIG. 3A

FIG. 1A illustrates a perspective view of a semiconductor device 100,according to some embodiments of the invention. Semiconductor device 100includes a MuGFET with multiple narrow fins having different widthsconnected in parallel between a source region and a drain region, a gatedielectric and multiple gates (top and sides of the fin) to improve thegate control compared to planar devices. Semiconductor device 100includes a substrate 102 that supports source/drain regions 104, 106,multiple fins 110, 111, 112, 113, a gate dielectric layer 114, and agate 108. Gate dielectric layer 114 is disposed over multiple fins 110,111, 112, and 113. In some embodiments, fins 110-113 have different finwidths. In some embodiments, the spacing S (see e.g. FIG. 3C throughFIG. 3H) between adjacent fins (such as 110-111, 111-112 and 112-113)are different to find a trade off for the vertical and lateral part ofthe gate resistance. Especially to compensate the lower gm due to anincreased source resistance in fins having smaller fin width with areduced gate resistance for constant overall gain the fin spacing shouldbe arranged that way that the fin spacing is increased towards smallerfin width. Source/drain regions 104, 106 includes source/drain contacts105, 107, respectively. Gate 108 is disposed over the gate dielectriclayer 114 and includes a gate contact 109.

FIG. 1B illustrates a perspective view of a semiconductor device 200having different fin widths and gate dimensions, according to someembodiments of the invention. Semiconductor device 200 includes asubstrate 102 that supports source/drain regions 104, 106, fins 110-113and gate 108. Additionally, semiconductor device 200 includes a gatedielectric 114 disposed on the top and the sides of fins 110-113. Gatedielectric 114 lies between a gate 108 and the fins 110-113. Having thegate to wrap around three sides of each of the fins provides forimproved gate control when compared to planar devices. In someembodiments, source/drain regions 104, 106 includes source/draincontacts 105, 107, respectively. In some embodiments, gate 108 includesa gate contact 109. In some embodiments, gate 108 includes gate segments220, 230, 240, 250 and 260. In some embodiments, gate segments 220, 230,240, 250 and 260 have different gate lengths (=channel lengths). In someembodiments, the fins 110-113 have different fin widths. In particularthere are two possible ways of arrangement. One can combine a small finwidth with a short channel length and a large fin width with a longchannel length. This option suppresses short channel effects thatinfluence the subthreshold slope. Another combination is to combine asmall fin width with a long channel length and a larger fin width with ashort channel length. This option allows for larger threshold voltagevariations from fin to fin. In some embodiments, the spacing betweenadjacent fins (such as 110-111, 111-112 and 112-113) is changing. Insome embodiments, the configuration such as that shown in FIG. 1A andFIG. 1B provides for multiple threshold voltage (Vt) values that canresult in the smoothening of transistor or varactor nonlinearities.Consequently, such an arrangement can be used for improved distortionbehaviour of a transistor or capacitance tuning behaviour of a varactor.

FIG. 2A illustrates a top view of a semiconductor device having fins310, 312, 314, 316, 318 and 320 with different fin widths connected inparallel to drain pads 306 and source pads 308, according to someembodiments of the invention.

FIG. 2B illustrates a top view of a semiconductor device havingdifferent fin widths and gate dimensions, according to some embodimentsof the invention. In FIG. 2B a FinFET device having different fin widthsWF1, WF2 and WF3 is combined with different gate lengths Lg1, Lg2 andLg3. The larger fin width WF is combined with the larger gate length Lg.This supports a tradeoff in the short channel effect with small gatelength and larger fin width. The largest gate length Lg1 is placed mostnear to the gate contact 109 and the smallest gate length Lg3 is placedmost far away from the gate contact 109. Such an arrangement combineshigher gm through smaller gate lengths with a higher gate resistanceleading to the same gain at RF frequencies for all parts of the devicehaving different fin width and being connected together.

FIG. 2C illustrates a top view of a semiconductor device havingdifferent fin widths and gate dimensions, according to some embodimentsof the invention. In FIG. 2C a FinFET device having different fin widthsWF1, WF2 and WF3 is combined with different gate lengths Lg1, Lg2 andLg3. The larger fin width WF is combined with the larger gate length Lg.This supports a tradeoff in the short channel effect with small gatelength and larger fin width. The largest gate length Lg3 is placed mostfar from the gate contact 109 and the smallest gate length Lg1 is placedmost near to the gate contact 109. Such an arrangement could lead to thesame gain at RF frequencies for all parts of the device having differentfin width WF depending on the values for the lateral (RL) and vertical(RV) part of the gate resistance.

FIG. 2D illustrates a top view of a semiconductor device havingdifferent fin widths and gate dimensions, according to some embodimentsof the invention. In FIG. 2D a FinFET device having different fin widthsWF1, WF2 and WF3 is combined with different gate lengths Lg1, Lg2 andLg3. The larger fin width WF is combined with the smaller gate lengthLg. This arrangement combines the lower drain/source resistance oflarger fin width WF with the higher transconductance gm of shorter gatelength Lg and lower parasitic gate to drain/source pad capacitance ofshorter gate length Lg. The largest gate length Lg3 is placed most farfrom the gate contact 109 and the smallest gate length Lg1 is placedmost near to the gate contact 109. Such an arrangement could lead to thesame gain at RF frequencies for all parts of the device having differentfin width WF depending on the values for the lateral (RL) and vertical(RV) part of the gate resistance.

FIG. 2E illustrates a top view of a semiconductor device havingdifferent fin widths and gate dimensions, according to some embodimentsof the invention. In FIG. 2E a FinFET device having different fin widthsWF1, WF2 and WF3 is combined with different gate lengths Lg1, Lg2 andLg3. The larger fin width WF is combined with the smaller gate lengthLg. This arrangement combines the lower drain/source resistance oflarger fin width WF with the higher transconductance gm of shorter gatelength Lg and lower parasitic gate to drain/source pad capacitance ofshorter gate length Lg. The smallest gate length Lg3 is placed most farfrom the gate contact 109 and the largest gate length Lg1 is placed mostnear to the gate contact 109. Such an arrangement could lead to the samegain at RF frequencies for all parts of the device having different finwidth WF depending on the values for the lateral (RL) and vertical (RV)part of the gate resistance.

All the devices in FIG. 1A through FIG. 2E can be arranged in asymmetric way with two gate contacts on opposite sides in the samemanner as converting the device of FIG. 3E into the device of FIG. 3F.

FIG. 3A illustrates a perspective view of a gate finger showing lumpedresistance elements modeling the gate resistance. When operating thegate finger at high frequencies the resistance of the gate finger needsto be represented by a distributed gate resistance network shown in FIG.3A consisting of lumped resistances lateral along the gate finger (RL)and vertical (RV) from top to bottom of the gate finger.

FIG. 3B illustrates a perspective view of a cross section throughmaterial stack of the gate finger of FIG. 3A, according to someembodiments of the invention. The gate finger usually consists of amaterial stack. The stack can consist of two, three or more differentmaterials. A conventional two material stack is poly silicon on top ofthe gate dielectric of the MOS device captured by an above silicidelayer. In high-k metal gate devices the gate material stack consists insome embodiments of a metal on top of the gate dielectric followed bypoly silicon which is caped by a silicide layer as shown in FIG. 3B.Between silicon and metal occurs an Schottky contact resistance thattogether with the conductivities of the materials of the stackestablishes a specific vertical gate resistance rv (with the unit of aresistance per area) leading to the vertical resistance RV shown in FIG.3A. Compared to this specific vertical gate resistance RV there existsalso a specific lateral gate resistance rl (with the unit of aresistance per length) leading to the lateral resistance RL shown inFIG. 3A that originates from the resistances of the silicide capinglayer in FIG. 3B which is connected by a gate contact.

FIG. 3C illustrates a top view of a semiconductor device, according tosome embodiments of the invention. In some embodiments, the device shownin FIG. 3C includes a portion of device 100 shown in FIG. 1. In someembodiments, the device shown in FIG. 3C includes fins F1, F2, F3 and F4having fin widths WF1, WF2, WF3, and WF4, respectively. Additionally,fin spacing S1 is the distance between fins F1 and F2; fin spacing S2 isthe distance between fins F2 and F3; fin spacing S3 is the distancebetween F3 and F4. Gate 108 is disposed over a gate dielectric layerprovided over the fins. The absolute value of the lateral gateresistance for one fin F of the FinFET device is proportional to thedistance of the fin from the gate contact. The absolute value of thevertical resistance RV for one fin is dependent on the area defined bythe gate length Lg and the spacing S of the fin to other fins. Asmentioned above by varying the fin widths of fins F1, F2, F3 and F4 theelectrical characteristics of the transistor structure can be altered.In some embodiments, the fin widths WF1, WF2, WF3 and WF4 are of equalwidths. In some embodiments, the semiconductor device shown in FIG. 3Cincludes at least two of the fins having different fin widths. In someembodiments, the fin spacing in the device is such that the fin spacingincreases with distance from the gate contact (=S 1<S2<S3) depending onthe values of the specific lateral (rv) and vertical (rl) resistance. Insome embodiments, the fin spacing in the device is decreases with thedistance from the gate contact (=S1>S2>S3) depending on the values ofthe specific lateral rl and vertical rv resistance.

FIG. 3D illustrates a top view of a semiconductor device having gatecontacts on two ends, according to some embodiments of the invention. Insome embodiments, the device shown in FIG. 3D includes a gate 308disposed over a gate layer provided over the fins. In some embodiments,gate 308 has gate contacts 309 on either ends of gate 308. In someembodiments, device shown in FIG. 3D includes fins F1, F2, F3, F4 and F5having fin widths WF21, WF22, WF3, WF12 and WF11, respectively. In someembodiments, fin widths WF11=WF12=WF21=WF22=WF3. In some embodiments,fin spacing S11 and S21 are equal and less than fin spacing S12 and S22,where S12=S22 depending on the values of the specific lateral (rv) andvertical (rl) resistance. In some embodiments, fin spacing S11 and S21are equal and larger than fin spacing S12 and S22, where S12=S22depending on the values of the specific lateral (rv) and vertical (rl)resistance.

FIG. 3E illustrates a top view of a semiconductor device havingdecreasing fin widths away from the gate contact, according to someembodiments of the invention. In some embodiments of the semiconductordevice shown in FIG. 3E, the fin width decreases (=WF1>WF2>WF3>WF4) andthe fin spacing increases with distance from that gate contact(=S1<S2<S3) depending on the values of the specific lateral (rv) andvertical (rl) resistance. In some embodiments of the semiconductordevice shown in FIG. 3E, the fin width decreases (=WF1>WF2>WF3>WF4) andthe fin spacing decreases (=S1>S2>S3) with distance from the gatecontact depending on the values of the specific lateral (rv) andvertical (rl) resistance.

FIG. 3F illustrates a top view of a semiconductor device having gatecontacts at opposite ends of the device and fin widths decreasingtowards the center of the device, according to some embodiments of theinvention. In some embodiments of the semiconductor device shown in FIG.3F, fin width WF11=WF21>WF12=WF22>WF3 and fin spacing S11=S21 and lessthan S22=S12. In some embodiments of the semiconductor device shown inFIG. 3F, fin width WF11=WF21>WF12=WF22>WF3 and fin spacing S11=S21 andmay be larger than S22=S12.

FIG. 3G illustrates a top view of a semiconductor device havingincreasing fin widths away from the gate contact, according to someembodiments of the invention. In some embodiments of the semiconductordevice shown in FIG. 3G, the fin widths increases (=WF1<WF2<WF3<WF4) andthe fin spacing increases (=S1<S2<S3) with increasing distance from thegate contact depending on the values of the specific lateral (rv) andvertical (rl) resistance. In some embodiments of the semiconductordevice shown in FIG. 3G, the fin widths increases (=WF1<WF2<WF3<WF4) andthe fin spacing decreases (=S1>S2>S3) with increasing distance from thegate contact depending on the values of the specific lateral (rv) andvertical (rl) resistance.

FIG. 3H illustrates a top view of a semiconductor device having gatecontacts at opposite ends of the device and fin widths increasingtowards the center of the device, according to some embodiments of theinvention. In some embodiments of the semiconductor device shown in FIG.3H, fin width WF11=WF21<WF12=WF22<WF3 and fin spacing S11=S21<S12=S22depending on the values of the specific lateral (rv) and vertical (rl)resistance. In some embodiments of the semiconductor device shown inFIG. 3H, fin width WF11=WF21<WF12=WF22<WF3 and fin spacingS11=S21>S12=S22 depending on the values of the specific lateral (rv) andvertical (rl) resistance.

In some embodiments the devices shown in FIG. 3C, FIG. 3D, FIG. 3E, FIG.3F, FIG. 3G and FIG. 3H combining different fin spacing with differentfin width can additionally combine different fin width WF with differentgate length Lg. Possible combinations of fin width WF with gate lengthLg can be found in FIG. 2B, FIG. 2C, FIG. 2D and FIG. 2E but are notlimited to this combinations.

Fin space variations in an integrated circuit may be introduced indifferent ways. For example, fin space variation may be introducedintentionally using a controlled process. This may be done, for example,by layout drawing or placement in different locations of the layout ofthe integrated circuit having different printing resolution or adedicated processing generating large local fin width mismatchvariations leading to different fin spacings. In an embodiment, thespacing between two fins may differ by more than 4 nm (nano meter). Inan embodiment, the spacing between two fins may differ by more than 5nm. In another embodiment, the spacing between two fins may differ bymore than 6 nm. In an embodiment, the spacing between two fins maydiffer by more than 7 nm. In an embodiment, the spacing between two finsmay differ by more than 5 nm. In an embodiment, the spacing between twofins may differ by more than 9 nm. In an embodiment, the spacing betweentwo fins may differ by more than 10 nm.

FIG. 4 illustrates a top view of a semiconductor device 400 having astepped fin-width structure, according to some embodiments of theinvention. In some embodiments, device 400 is included as a portion ofdevice 100 shown in FIG. 1A. In some embodiments, device 400 includes asubstrate region 402-405 that supports a fin structure 406. In someembodiments, fin structure 406 includes a first segment 407 and a secondsegment 408. In some embodiments, the width of the first segment 408 islarger than the width of the second segment 407. In some embodiments,one end of first segment 407 is coupled to a source region (not shown inFIG. 4) and one end of the second segment 408 is coupled to the drainregion (not shown in FIG. 4) and the remaining ends of first and secondsegments 407, 408 are coupled to each other. In some embodiments, oneend of first segment 407 is coupled to a drain region and one end of thesecond segment 408 is coupled to the source region and the remainingends of first and second segments 407, 408 are coupled to each other. Insome embodiments gate 410 is disposed over a dielectric layer overlayingon top of fin structure 406. As shown in FIG. 4, the two different finwidths (for fin segments 407 and 408) can be used to generate twochannel regions with different threshold voltages, drain and sourceresistances and flicker noise because flicker noise of drain currentdepends on noise contributions along the channel length and possiblyadditionally also on mobility if fins with different crystal orientationin top and sidewall surface are used. These features can be used toprovide improved output conductance, transconductance and improvedsignal to noise ratio.

The multiple fin width devices described above connecting fin segmentswith different fin widths in series can be combined with a split gatestructure combining different gate length with different fin width. Someembodiments combine a short gate length (channel length) on a wider finconnected to the source while having the longer gate length (channellength) running over the narrower fin on the drain side providing lowersource resistance and higher gm compared to a narrow fin only device andlower output conductance compared to a wide fin only device. Otherembodiments combine a long gate length over the wider fin as a firstpart and a short gate length over the narrower fin as a second part ofthe split gate structure. Some embodiments connect the first part to thesource and second part to the drain. Some embodiments connect the firstpart to the drain and second part to the source. The use of a specialcombination of fin width and gate length (=channel length) depends onweather the threshold voltage increases with a wider fin due to bodydepletion charge or a narrower fin due to short channel effects(affecting e.g. the subthreshold slope) and the increase of thresholdvoltage with shorter gate length due to halos or the decrease of thethreshold voltage with shorter gate length due to short channel effects.

FIG. 13 illustrates generally an example semiconductor device 1300.Semiconductor device 1300 can include a MuGFET with multiple fins havingdifferent widths connected in parallel between a source region and adrain region, a gate dielectric and multiple gates (top and sides of thefin) to improve the gate control compared to planar devices.Semiconductor device 1300 can include a substrate 1302 that supportssource/drain regions 1304, 1306, multiple fins 1310, 1311, 1312, 1313, agate dielectric layer 1314, and a gate 1308. Gate dielectric layer 1314can be disposed over multiple fins 1310, 1311, 13312, and 113. In someembodiments, fins 1310-1313 have different fin widths. In someembodiments, the spacing S (see e.g. FIG. 3C through FIG. 3H) betweenadjacent fins (such as 1310-1311, 1311-1312 and 1312-1313) are differentto find a trade off for the vertical and lateral part of the gateresistance. To compensate the lower gm due to an increased sourceresistance in fins having smaller fin width with a reduced gateresistance for constant overall gain, the fin spacing should be arrangedthat way such that the fin spacing is increased towards smaller finwidth. In some embodiments, gate 1308 includes gate segments 1320, 1330,1340, 1350 and 1360. In some embodiments, gate segments 1320, 1330,1340, 1350 and 1360 have different gate lengths (=channel lengths). Insome embodiments, the fins 1310-1313 have different fin widths.Source/drain regions 1304, 1306 includes source/drain contacts 1305,1307, respectively. Gate 1308 can be disposed over the gate dielectriclayer 1314 and can include one or more gate contacts 1309. In variousembodiments, a first fin 1310 can include a stepped fin-width structure.In some embodiments, the first fin 1310 can include a first segment 1357and a second segment 1358. In some embodiments, the width of the firstsegment 1357 is larger than the width of the second segment 1358. Insome embodiments, one end of first segment 1357 can be coupled to afirst source/drain region 1304 and one end of the second segment 1358can be coupled to a second source drain region 1306 and the remainingends of first and second segments 1357, 1358 can be coupled to eachother under a gate segment 1360.

The split gate structure can be applied also to the multiple fin widthdevices connecting fins with different fin width in parallel (e.g. FIG.2A) combining the good gain gm/gds of the self-cascoding split gatestructure with the good linearity of the multi fin width device.

FIG. 5 illustrates a top view of a semiconductor device 500 having astepped fin-width structure along with a split gate structure, accordingto some embodiments of the invention. In some embodiments, device 500 isincluded as a portion of device 100 shown in FIG. 1A. In someembodiments, device 500 includes a substrate region 501-505 thatsupports a fin structure 506 and a split gate 510. In some embodiments,fin structure 506 includes a first fin segment 507, and a second finsegment 508. In some embodiments, the width of the first fin segment 508is larger than the width of the second fin segment 507. In someembodiments, split gate 510 includes a first gate segment 512 and asecond gate segment 514. In some embodiments, the first gate segment 512and the second gate segment 514 are electrically coupled at both endsusing coupling gate segments 516 and 518. In some embodiments, firstgate segment 512 has a gate length “Lg1” and the second gate segment hasa gate length “Lg2”. In some embodiments, the first gate segment 512 andsecond gate segment 514 are electrically coupled at one end andelectrically isolated at the other end. In some embodiments, first gatesegment 512 of split gate 510 is disposed on top of first fin segment507 of fin 506. In some embodiments, second gate segment 514 of splitgate 510 is disposed on top of second fin segment 508 of fin 506. Insome embodiments, the first gate segment 512 has a larger gate length“Lg1” than the second gate segment 514 with a gate length “Lg2”.Advantages of gate segmentation provided as shown in FIG. 5 includesavoiding the scenario of disposing of gate 510 in the active region ofthe transistor where the fin edges of the first segment 507 meet the finedges of the second segment 508. The regions not covered by a gate and aspacer maybe receive a drain/source implant.

The split gate structure can be arranged asymmetrically with respect todrain and source. Some embodiments having the first part of the splitgate near the source for reduced source resistance. Some embodimentshaving the first part of the split gate far from the source for reducedgate to source capacitance. Some embodiments having the second part ofthe split gate far from the drain for reduced gate to drain (miller)capacitance. The corresponding larger drain resistance in this case isacceptable due to its small effect on transcondetance when the device isoperated in saturation.

The device of FIG. 5 can also combine a first N-type or P-type device,for example an NMOS or PMOS transistor having the narrow fin in serieswith a second NMOS transistor having the wider fin or vice versa. (e.g.providing the first device as a NMOS cascode device or a PMOS currentsource and the other as a NMOS switching or amplifying device). In someembodiments of FIG. 5, both gates segments 512 and 514 can be connectedto the same signal (e.g. used in self cascoding devices). In someembodiments of FIG. 5, both gates of the split gate can be connected todifferent signals (e.g. used in cascode or mixer circuits).

FIG. 6A illustrates a top view of a semiconductor device 600 having astepped fin structure, according to some embodiments of the invention.In some embodiments, device 600 is included as a portion of device 100shown in FIG. 1A. In some embodiments, device 600 includes a substrateregion 602-605 that supports a fin structure 606 and a gate 612. In someembodiments, fin structure 606 includes a first fin segment 607, asecond fin segment 608 and a third fin segment 610. In some embodiments,the first fin segment 607 and the third fin segment 610 haveapproximately the same width. In some embodiments, the second finsegment 608 has a width that is smaller than at least one of first finsegment 607 and third fin segment 610. In some embodiments, the gate 612is disposed over a portion of fin structure 606 such that all sides ofsecond fin segment 608 is covered with the gate material that forms gate612. Additionally, the gate 612 is disposed over the fin structure 606such that it lays over equal portions of the first fin segment 607 andthe third fin segment 610.

In some embodiments, larger fin width of the fins can be also used toreduce the source and drain series resistance, and it is also possibleto combine this resistance reduction with an asymmetric channel havingmodulated threshold voltage along the channel length. Because flickernoise has different contributions along channel length to the totalamount of drain current noise and flicker noise depends on localthreshold voltage and effective crystal orientation of top and sidewallsurfaces of fin along the channel, modulation of fin width along channellength can tailor noise contributions along channel length resulting inreduced total amount of flicker noise. In some embodiments, reduceddrain/source series resistance can be obtained by using wider fins inthe outer regions of fin structure 606.

FIG. 6B illustrates a top view of a semiconductor device 600 having astepped fin structure with a broad fin width in the center of the fin,according to some embodiments of the invention. In some embodiments,device 600 is included as a portion of device 100 shown in FIG. 1A. Insome embodiments of the semiconductor device shown in FIG. 6B, the finhas three sections, a first section having a width WF2, a second sectionhaving width WF3 and a third section with fin width WF1. In someembodiments, a gate structure 612 overlaps completely the second sectionof the fin and a portion of the first section and the third section ofthe fin. FIG. 6B presents somehow the inverted structure of FIG. 6Ahaving narrow fins segments at drain (WF2) and source (WF1) and a finsection with larger fin width WF3 compared to fin segments connected todrain and source in the center of the multiple fin width deviceconnecting different fin width in a series connection. In someembodiments, WF3>WF2 and WF3>WF1. In some embodiments, WF3>WF2 andWF3>WF1 and WF1>WF2. In some embodiments, WF3>WF2=WF1.

FIG. 6C illustrates a top view of a semiconductor device having astepped fin structure having sections with different fin widths andseparate gates for each of the different fin sections, according to someembodiments of the invention. In some embodiments, device 600 isincluded as a portion of device 100 shown in FIG. 1A. In someembodiments of the semiconductor device shown in FIG. 6C, the fin hasthree sections, a first section having a width WF2, a second sectionhaving width WF3 and a third section with fin width WF1. In someembodiments, a gate structure having section 614, 616 and 618 overlapportions of the fin such that 614 overlaps a portion of the firstsection, 616 overlaps the a portion of the second section and 618overlaps a portion of the third section. In some embodiments, WF3>WF2and WF3>WF1. In some embodiments, WF3>WF2 and WF3>WF1 and WF1>WF2. Insome embodiments, WF3>WF2=WF1.

FIG. 6D illustrates a top view of a semiconductor device 600 having astepped fin structure with a broad fin width in the center of the finand tapered transitions from the broad central fin to the narrower outerfin parts, according to some embodiments of the invention. In someembodiments, device 600 is included as a portion of device 100 shown inFIG. 1. In some embodiments of the semiconductor device shown in FIG.6D, the fin has three sections, a first section having a width WF2, asecond section having width WF3 and a third section with fin width WF1.In some embodiments, a gate structure 612 overlaps completely the secondsection of the fin and a portion of the first section and the thirdsection of the fin. The transition from the central broad second finsection with fin width WF3 towards the more narrower first and thirdouter fin sections with fin widths WF2 and WF2 is arranged in an angledor tapered way. In some embodiments, WF3>WF2 and WF3>WF1. In someembodiments, WF3>WF2 and WF3>WF1 and WF1>WF2. In some embodiments,WF3>WF2=WF1.

FIG. 7 illustrates the semiconductor device shown in FIG. 6A with a gatehaving a skewed gate arrangement disposed on the fin, according to someembodiments of the invention. In some embodiments, device 700 isincluded as a portion of device 100 shown in FIG. 1A. In someembodiments, device 700 includes a substrate region 702-705 thatsupports a fin structure 706 and a gate 710. In some embodiments, finstructure 706 includes a first fin segment 707 and a second fin segment708 coupled by a third fin segment 709. In some embodiments, the firstfin segment 707 and the second fin segment 708 have approximately thesame width. In some embodiments, the third fin segment 709 has a widththat is smaller than at least one of first fin segment 707 and secondfin segment 708. In some embodiments, the gate 710 is disposed over aportion of fin structure 706 such that the three sides (top, left,right) of third segment 709 formed above the substrate is covered by thegate 710. Additionally, the gate 710 is disposed over fin structure 706in such a way that the gate covers a greater portion of one of the firstor second segments over the other segment. In other words the gate 710lies over the fin structure 706 in a skewed or asymmetrical manner tocreate an asymmetric channel.

Referring to FIG. 4 through FIG. 7 (as well as FIG. 10), it is notedthat the transition from one fin width to another fin width may begradual as opposed to being abrupt. It is also noted that, in one ormore embodiments, the fin width may change a plurality of times. Suchvarying fin widths may be referred to as multiple modulated fin widths.

FIG. 8A illustrates a semiconductor device 800 showing a fin structurehaving a tapered section, according to some embodiments of theinvention. In some embodiments, device 800 is included as a portion ofdevice 100 shown in FIG. 1A. In some embodiments, device 800 includes asubstrate region 802-805 that supports a fin structure 806 and a gate810. In some embodiments, fin structure 806 includes a first fin segment807 and a second fin segment 808 coupled by a third fin segment 809. Insome embodiments, the first fin segment 807 and the second fin segment808 have approximately the same width. In some embodiments, the firstfin segment 807 has a different width compared to the second fin segment808. In some embodiments, the third fin segment 809 couples the firstfin segment 807 and second fin segment 808 and has a structure having awidth tapering between the first fin segment 807 and the second finsegment 808. In some embodiments, the gate 810 is disposed over aportion of fin structure 806 such that the three sides of third segment809 formed above the substrate is covered by the gate 810. In someembodiments, the gate 810 is disposed over fin structure 806 in such away that the gate covers a greater portion of one of the first (807) orsecond (808) segments over the other segment. In other words the gate810 lies over the fin structure 806 in a skewed or asymmetrical mannerto create an asymmetric channel. In some embodiments, the gate 810 isdisposed over the fin structure 806 such that it lays over an equalportion of first fin segment 807 and a second fin segment 808. In someembodiments, providing for a graded channel width (=fin width) as shownin FIG. 8A allows for better electrical performance.

FIG. 8B illustrates a top view of a semiconductor device showing a finstructure having a tapered section, according to some embodiments of theinvention. In some embodiments, device 800 is included as a portion ofdevice 100 shown in FIG. 1A. As shown in FIG. 8B the gate structure overthe fin is located a distance “d” from a source/drain region attached tothe fin.

FIG. 9 illustrates a semiconductor device 900 showing a fin structurehaving a curved section, according to some embodiments of the invention.In some embodiments, device 900 is included as a portion of device 100shown in FIG. 1A. In some embodiments, device 900 includes a substrateregion 902-905 that supports a fin structure 906 and a gate 910. In someembodiments, fin structure 906 includes a first fin segment 907 and asecond fin segment 908 coupled by a third fin segment 909. In someembodiments, the first fin segment 907 and the second fin segment 908have approximately the same width. In some embodiments, the first finsegment 907 has a different width compared to second fin segment 908. Insome embodiments, the third fin segment 909 includes a curved structurethat couples the first fin segment 907 and the second fin segment 908 asshown in FIG. 9. In some embodiments, the gate 910 is disposed over aportion of fin structure 906 such that the three sides of third segment909 formed above the substrate is covered by the gate 910. In someembodiments, the gate 910 is disposed over fin structure 906 in such away that the gate covers a greater portion of one of the first andsecond segments over the other segment. In other words the gate 910 liesover the fin structure 906 in a skewed or asymmetrical manner to createan asymmetric channel. In some embodiments, the gate 910 is disposedover the fin structure 906 such that it lays over an equal portion offirst fin segment 907 and a second fin segment 908. In some embodiments,the gate 910 covers part of second segment 908 and third segment 909 butnot first segment 907.

FIG. 10 illustrates a top view of a semiconductor device 1000 showingmultiple fins having a stepped fin structure and multiple gatesoverlying the fins, according to some embodiments of the invention. Insome embodiments, semiconductor device 1000 includes a substrate 1002having a source/drain region 1006, 1004 disposed over it. Additionally,fins 1010, 1013 and 1015 are disposed on substrate 1002 and coupledbetween source/drain regions 1006, 1004. In some embodiments, gates 1017and 1018 are disposed over fins 1010, 1013 and 1016. In someembodiments, gate length Lg₁ of gate 1017 (=part of channel length oftransistor) is different compared to the gate length Lg₂ of gate 1018.In some embodiments, gate 1017 is disposed at a distance “d1” fromsource/drain region 1004. In some embodiments, gate 1018 is disposed ata distance “d2” from source/drain region 1006. In some embodiments,d1>d2. In some embodiments, d1<d2. By such an asymmetric device throughan unequal distance (d1 not equal to d2) of gate to source pad and gateto drain pad, source resistance or capacitance can be lowered andadditionally drain (miller-) capacitance can be lowered. In someembodiments, distance of gate 1017 to drain pad 1004 is larger than gate1018 to source pad 1006. By that the drain gate miller capacity isreduced and the source resistance is kept low. The regions not coveredby a gate and a spacer maybe receive a drain/source implant. Fin 1010includes a first segment 1008 coupled to a second segment 1009.Similarly, fins 1013, 1016 includes first segments 1011, 1014 coupled toa second segment 1012, 1015, respectively. In some embodiments, thefirst segment 1008 of fin 1010 has a different width and length comparedto first segment 1011 of fin 1013. In some embodiments, the secondsegment 1009 of fin 1010 has a different width and length compared tosecond segment 1012 of fin 1013.

In some embodiments, for the various embodiments described above, thetop and sidewall surfaces of the fin structure can have differentcrystal orientation (such as indicated by the miller indices 100, 110,010, 001, 101, etc. for crystal surface orientation) that can result indifferent mobility and different flicker noise when changing the finwidth which can result in improved signal to noise ratio.

In some embodiments different fin widths are included in different partsof an integrated circuit and devices are connected via metallization ofthe used technology. Devices having different fin widths need not to beplaced nearby when connected in series or parallel connection. In someparts of the integrated circuit, devices having wider fin widths maybedesired and in other parts of the integrated circuit, devices withnarrower fins may be preferred.

FIG. 11 illustrates a top view of two semiconductor devices coupled inseries with each device having different fin widths, according to someembodiments of the invention. The fins F11, F12, F13, F14 and F15 canhave same fin width or different fin width but at least one fin from thegroup of fins F11, F12, F13, F14 and F15 has a fin width different fromthe fin widths of the group F21, F22, F23, F24 and F25. The samestatement is valid for the group of fins F21, F22, F23, F24 and F25 withrespect to the group of fins F11, F12, F13, F14 and F15.

In some embodiments more than two devices having different fin widthsare connected in series (e.g. current source, mixing stage and cascodestage in a gilbert type mixer circuit).

FIG. 12A illustrates a top view of two semiconductor devices havingdifferent fin widths WF1 and WF2 coupled in parallel and showing ashared gate between the two devices, according to some embodiments ofthe invention. In some embodiments more than two devices havingdifferent fin widths are connected together in parallel. In someembodiments, one group A of fins having same fin width and connected inparallel are connected in parallel with another group B of fins havingsame fin widths but different from the fin width of group A. In someembodiments more than two devices with grouped fins in parallel areconnected in parallel.

FIG. 12B illustrates a top view of two semiconductor devices havingdifferent fin widths WF1 and WF2 coupled in parallel with separate gatescontrolling the devices, according to some embodiments of the invention.In some embodiments more than two devices having different fin widthsare connected together in parallel. In some embodiments, one group A offins having same fin width and connected in parallel are connected inparallel with another group B of fins having same fin widths butdifferent from the fin width of group A. In some embodiments more thantwo devices with grouped fins in parallel are connected in parallel.

The accompanying drawings that form a part hereof show by way ofillustration, and not of limitation, specific embodiments in which thesubject matter may be practiced. The embodiments illustrated aredescribed in sufficient detail to enable those skilled in the art topractice the teachings disclosed herein. Other embodiments may beutilized and derived therefrom, such that structural and logicalsubstitutions and changes may be made without departing from the scopeof this disclosure. This Detailed Description, therefore, is not to betaken in a limiting sense, and the scope of various embodiments isdefined only by the appended claims, along with the full range ofequivalents to which such claims are entitled.

Such embodiments of the inventive subject matter may be referred toherein, individually and/or collectively, by the term “invention” merelyfor convenience and without intending to voluntarily limit the scope ofthis application to any single invention or inventive concept if morethan one is in fact disclosed. Thus, although specific embodiments havebeen illustrated and described herein, it should be appreciated that anyarrangement calculated to achieve the same purpose may be substitutedfor the specific embodiments shown. This disclosure is intended to coverany and all adaptations or variations of various embodiments.Combinations of the above embodiments, and other embodiments notspecifically described herein, will be apparent to those of skill in theart upon reviewing the above description. In the previous discussion andin the claims, the terms “including” and “comprising” are used in anopen-ended fashion, and thus should be interpreted to mean “including,but not limited to . . . ”.

The Abstract of the Disclosure is provided to comply with 37 C.F.R.§1.72(b), requiring an abstract that will allow the reader to quicklyascertain the nature of the technical disclosure. It is submitted withthe understanding that it will not be used to interpret or limit thescope or meaning of the claims. In addition, in the foregoing DetailedDescription, it can be seen that various features are grouped togetherin a single embodiment for the purpose of streamlining the disclosure.This method of disclosure is not to be interpreted as reflecting anintention that the claimed embodiments require more features than areexpressly recited in each claim. Rather, as the following claimsreflect, inventive subject matter lies in less than all features of asingle disclosed embodiment. Thus the following claims are herebyincorporated into the Detailed Description, with each claim standing onits own as a separate embodiment.

1. A transistor comprising: a source region; a drain region; a first finextending between the source region and the drain region, wherein thefirst fin has a first fin width coupled in series with a second finwidth, the second fin width different from the first fin width; and agate configured to control current flow through the first fin.
 2. Thetransistor of claim 1 wherein the transistor includes a p-typetransistor.
 3. The transistor of claim 1, wherein the transistorincludes an n-type transistor
 4. The transistor of claim 1 wherein theseries coupled fin widths include a curved shape.
 5. The transistor ofclaim 1 wherein the series coupled fin widths include a tapered shape.6. The transistor of claim 1, wherein the gate overlaps the first finwidth and the second fin width.
 7. The transistor of claim 1, whereinthe gate overlaps the first fin width and the second fin widthasymmetrically.
 8. The transistor of claim 1, including a pair of gatecontacts disposed on opposite sides of the first fin.
 9. The transistorof claim 1 including a second fin connected in parallel with the firstfin between the source region and the drain region, and wherein the gateis configured to control current flow through the second fin
 10. Thetransistor of claim 1, including a gate contact, wherein at least onegate length and at least one fin width increases as a function ofdistance from the gate contact.
 11. The transistor of claim 10, whereinthe second fin includes a third fin width; wherein the third fin widthis different from the first fin width; and wherein the third fin widthis different from the second fin width.
 12. The transistor of claim 1,wherein the gate includes a split gate, the split gate including: afirst segment disposed over a first fin width; a second segment disposedover a second fin width; and an opening, defined by the first segmentand the second segment, disposed over an area of the fin where fin edgescorresponding to the first fin width meet fin edges corresponding to thesecond fin width.
 13. The transistor of claim 12, wherein the opening isdisposed asymmetrically over the area where the fin edges correspondingto the first fin width meet the fin edges corresponding to the secondfin width.
 14. The transistor of claim 1, wherein the first fin width ispositioned under the gate, a portion of the second fin width ispositioned under the gate, a portion of a third fin width is positionedunder the gate, and the second fin and the third fin width are less thanthe first fin width to reduce flicker noise.
 15. The transistor of claim14, wherein the second fin width is substantially equal to the third finwidth.
 16. The transistor of claim 14, wherein the second fin width isgreater than the third fin width.
 17. The transistor of claim 14,wherein the gate is configured to overlie substantially equal portionsof the second fin width and the third fin width.
 18. The transistor ofclaim 14, wherein the gate is configured to asymmetrically overlie theportions of the second and third fin widths.
 19. The transistor of claim1, wherein the first fin width is positioned under the gate, a portionof the second fin width is positioned under the gate, a portion of athird fin width is positioned under the gate, and the second fin and thethird fin width are greater than the first fin width to reduce flickernoise.
 20. The transistor of claim 19, wherein the gate is configured toasymmetrically overlie the portions of the second and third fin widths.